Artificial intelligence is beginning to change how semiconductor engineers build chips, from generating RTL and testbenches to managing verification workflows. But faster generation creates a fundamental engineering question: how can teams know that what AI produces actually matches what the chip was supposed to do?
VerifAIX is tackling that problem with an AI based verification platform designed to connect specifications, implementations and verification evidence. The company has raised $5 million in seed funding co led by Endiya Partners and Bluehill VC to develop the technology and expand its engineering and customer operations across the US, India and Israel.
The difficulty is not simply having more code or more components to test. Modern chips combine increasingly complex architectures, protocols, interfaces and software defined functionality. Engineers need to establish that those pieces behave according to the original design requirements, including edge cases that may not be obvious from the implementation itself.
Only 14% of ASICs were functionally correct and manufacturable on the first attempt, according to data from the 2024 Wilson Research Group IC/ASIC Functional Verification Trends cited by Semiconductor Engineering.
AI can help reduce the amount of manual work involved in verification, but generating more verification artifacts does not necessarily establish that the underlying design is correct.
That distinction becomes particularly important as AI begins generating parts of the design itself.
VerifAIX’s platform approaches the problem from the specification level. Its “Formal Brain” combines AI reasoning with mathematically grounded methods to understand specifications and intended behavior.
Rather than allowing each verification task to operate independently, the system is designed to create a common understanding of the specification, design implementation and verification assets. This allows it to identify gaps and inconsistencies and use that understanding across formal verification, simulation, coverage and debugging.
Turning design intent into verification evidence
The company says its platform can work across the verification lifecycle, from specifications through verification closure.
Its agents can generate verification plans, testbenches and assertions while maintaining traceability to the requirements behind them. The system can also use existing EDA tools to execute formal and simulation workflows and help identify the causes of failures.
That approach is particularly relevant to AI generated hardware because an AI system should not necessarily be the final authority on whether its own output is correct.
“AI is changing how semiconductor designs are created, but generating a design is not the same as proving that it is correct,” said Madhulima Tewari, CEO of VerifAIX. “The industry urgently needs an independent layer of trust that can establish correctness and preserve traceability to design intent, and we’re building that. This funding enables us to deepen the technology, expand our engineering capabilities and take the platform to increasingly complex designs and a growing set of customers.”
The broader semiconductor market is moving in the same direction. Cadence has introduced AI based tools that automate parts of chip design and verification, including RTL development, testbench creation, verification planning, regression management and debugging.
As those systems become capable of completing more engineering tasks, verification could increasingly become the layer that determines whether AI generated work is ready to move forward.
For VerifAIX, that means combining the flexibility of AI with formal methods that can provide a more rigorous basis for establishing correctness.
The goal is not simply to verify chips faster. It is to create a way for engineers to understand what was generated, why it should be correct and how that conclusion can be traced back to the original design intent.
